There has been an interrupt control technique as one of control techniques for responding to an event which takes place inside or outside a data processor. In interrupt control, when various kinds of causes of interrupt arise, an interrupt controller controls their acceptance according to the priority levels and interrupt mask levels. Then, the controller identifies the accepted cause of interrupt, and requests an interruption of a central processing unit. When having received the request for interruption, the central processing unit performs a process for saving the last states of an internal register and others into a memory, and then fetches a vector depending on the cause of interrupt, and runs an fetched interrupt-processing program. As described above, arbitration by the interrupt controller and the save process by the central processing unit are required between the occurrence of a cause of interrupt and the execution of a process to respond to the cause of interrupt, and therefore it takes time until interrupt processing is started. In addition, frequent occurrences of such interrupt process increase the load on the central processing unit.
In search for publicly known examples after the invention was made, the following patent documents were found. One of them, JP-A-7-105124, discloses that it is made possible to offer all of interrupt request sources an opportunity to execute interruption equally by adoption of a set of interrupt request arbiter circuits connected in an annular form so that the priority of interrupt can be shifted. Further, JP-A-64-55667 discloses that interrupt-processing units connected in the form of a daisy chain are arranged so that they can judge in advance whether their own interrupt requests have been authorized or not when receiving direct inputs of interrupt-authorizing signal and interrupt acceptance level signal from the central processing unit, whereby the judgment concerning whether interrupt is permitted or not can be speeded up.